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CXD2408AR timing generator for progressive scan ccd image sensor description the CXD2408AR is an ic developed to generate the timing pulses required by the progressive scan ccd image sensors as well as signal processing circuits. features eia support electronic shutter function random trigger shutter function sync signal generator supports external synchronization supports non-interlaced operation base oscillation 1560fh (24.5454mhz) applications progressive scan ccd cameras structure silicon gate cmos ic applicable ccd image sensors icx074ak, icx074al absolute maximum ratings supply voltage v dd v ss ?0.5 to +7.0 v input voltage v i v ss ?0.5 to v dd + 0.5 v output voltage v o v ss ?0.5 to v dd + 0.5 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage v dd 4.75 to 5.25 v operating temperature topr ?0 to +75 ? ?1 e96402a68 sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 64 pin lqfp (plastic)
?2 CXD2408AR block diagram rg xh1 xh2 xshp xshd xrs xv1 xv2 xv3 xsg xhhg1a xhhg1b xhhg2 xvog xvhold tg pulse generator output control v-control v-decoder 1/525 1/390 h-decoder counter decode 1/2 gate test circuit gate cki osco osci trig ps ed0 ed1 ed2 smd1 smd2 test7 test6 test5 vri hri cl cld o2fh fld blk sync hdo vdo hdi vdi ext rend revh octl rdm rm xcpdm xcpob pblk id wen xsub 24.5mhz v ss v ss v ss v ss v dd v dd 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 33 41 42 43 44 45 46 47 test8 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 1 test4 32 test2 21 test1 20 nc test3 31
3 CXD2408AR pin configuration test4 test3 xrs xshd xshp xsg xv1 xv2 v dd v ss xv3 test2 test1 xvhold xvog xhhg2 cl cld o2fh nc fld blk v ss v dd sync hdi vdi hdo vdo hri vri cki osco osci ps ed0 ed1 ed2 smd1 v ss smd2 trig rg xsub xh1 xh2 xhhg1a xhhg1b test8 wen id pblk xcpob xcpdm rm rdm v ss octl revh rend ext test7 test6 test5 CXD2408AR (g/a) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 1
4 CXD2408AR pin description pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 osco osci ps ed0 ed1 ed2 smd1 vss smd2 trig rg xsub xh1 xh2 xhhg1a xhhg1b xhhg2 xvog xvhold test1 test2 xv3 vss v dd xv2 xv1 xsg xshp xshd xrs test3 test4 test5 test6 test7 o i i i i i i i i o o o o o o o o o o o o o o o o o o o o o o i inverter output for oscillation. inverter input for oscillation. switching for electronic shutter speed input method. (with pull-down resistor) low: parallel input, high: serial input shutter speed setting. strobe input for serial mode. (with pull-up resistor) shutter speed setting. clock input for serial mode. (with pull-up resistor) shutter speed setting. data input for serial mode. (with pull-up resistor) shutter mode setting. (with pull-up resistor) gnd shutter mode setting. (with pull-up resistor) trigger input for random trigger shutter. reset gate pulse output. ccd discharge pulse output. clock output for ccd horizontal register drive. clock output for ccd horizontal register drive. clock output for transfer between ccd horizontal registers. clock output for transfer between ccd horizontal registers. clock output for transfer between ccd horizontal registers. clock output for transfer from ccd vertical register to ccd horizontal register. clock output for adjusting timing of transfer to ccd horizontal register. test output. normally open. test output. normally open. clock output for ccd vertical register drive. gnd power supply. clock output for ccd vertical register drive. clock output for ccd vertical register drive. ccd sensor charge readout pulse output. precharge level sample-and-hold pulse. data sample-and-hold pulse. sample-and-hold pulse. test output. normally open. test output. normally open. test output. normally open. test output. normally open. test input. set at low in normal operation. (with pull-down resistor) symbol i/o description
5 CXD2408AR pin no. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ext rend revh octl vss rdm rm xcpdm xcpob pblk id wen test8 cl cld o2fh nc fld blk vss v dd sync hdi vdi hdo vdo hri vri cki i i i i i i o o o o o i o o o o o o i i o o i i i internal synchronization/external synchronization switching. (with pull-down resistor) low: internal synchronization, high: external synchronization normal reset/direct reset switching. (with pull-down resistor) low: normal reset, high: direct reset v reset/hv reset switching. (with pull-down resistor) low: v reset, high: hv reset o2fh output control. (with pull-down resistor) low: no output, high: output gnd normal operation/random trigger shutter switching. (with pull-down resistor) low: normal operation, high: random trigger shutter switching for output mode. (with pull-down resistor) low: non-interlaced, high: interlaced clamp pulse output. clamp pulse output. blanking cleaning pulse output. line identification output. write enable output. test input. (with pull-down resistor) fck clock output. (0 ) fck clock output. (180 ) 2 fh output. field pulse output. composite blanking output. gnd power supply. composite sync output. horizontal sync signal input. vertical sync signal input. horizontal sync signal output. vertical sync signal output. horizontal reset signal input. vertical reset signal input. 2 fck clock input. symbol i/o description
6 CXD2408AR electrical characteristics dc characteristics (v dd = 4.75 to 5.25v, topr = 20 to +75 c) item supply voltage input voltage 1 (input pins other than those below) input voltage 2 (pins 7, 9, 10, 58, 59, 62, 63, and 64) output voltage 1 (output pins other than those below) output voltage 2 (pins 28, 29, 30, 31, 32, 33, 34, 49 and 50) output voltage 3 (pins 11, 13, and 14) output voltage 4 (pin 1) feedback resistor pull-up resistor pull-down resistor current consumption v dd v ih1 v il1 v ih2 v il2 v oh1 v ol1 v oh2 v ol2 v oh3 v ol3 v oh4 v ol4 r fb r pu r pd i dd i oh = 2ma i ol = 4ma i oh = 4ma i ol = 8ma i oh = 12ma i ol = 12ma i oh = 12ma i ol = 12ma v in = vss or v dd v il = 0v v in = v dd v dd = 5v icx074al in normal operating state 4.75 0.7v dd 0.7v dd 0.8 0.8 v dd 0.8 v dd /2 250k 5.0 1m 50k 50k 35 5.25 0.3v dd 0.3v dd 0.4 0.4 0.4 v dd /2 2.5m v v v v v v v v v v v v v ? ? ? ma symbol conditions min. typ. max. unit i/o pin capacitances (v dd = v i = 0v, f m = 1mhz) item input pin capacitance output pin capacitance c in c out 9 11 pf pf symbol min. typ. max. unit
7 CXD2408AR ac characteristics 1) phase characteristics of xh1, rg, xshp, xshd, xrs, cl, and cld ck xh1 rg xshp xshd xrs cl cld tck vpp/2 0.7v dd 0.3v dd 0.3v dd 0.7v dd 0.3v dd 0.3v dd 0.3v dd 0.3v dd 0.3v dd 0.7v dd 0.7v dd 0.7v dd 0.7v dd 0.7v dd tpd1 tpd2 tpd3 tpd4 tpd5 tpd13 tpd11 tpd9 tpd7 tpd8 tpd6 tpd14 tpd12 tpd10 symbol t ck t pd1 t pd2 t pd3 t pd4 t pd5 t pd6 t pd7 t pd8 t pd9 t pd10 t pd11 t pd12 t pd13 t pd14 ck cycle xh1 rising delay, activated by the falling edge of ck xh1 falling delay, activated by the falling edge of ck rg falling delay, activated by the rising edge of ck rg rising delay, activated by the falling edge of ck xshp falling delay, activated by the rising edge of ck xshp rising delay, activated by the falling edge of ck xshd falling delay, activated by the rising edge of ck xshd rising delay, activated by the falling edge of ck xrs falling delay, activated by the falling edge of ck xrs rising delay, activated by the rising edge of ck cl falling delay, activated by the rising edge of ck cl rising delay, activated by the rising edge of ck cld falling delay, activated by the rising edge of ck cld rising delay, activated by the falling edge of ck 41 28 29 27 33 36 30 36 29 34 28 15 17 30 33 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns definition typ. unit (v dd = 5.0v, topr = 25 c, load capacity of cl and cld = 30pf, load capacity of xh1, xshp, xshd, xrs, and rg = 10pf)
8 CXD2408AR xh1 rg 0.9v dd 0.1v dd tfh1 trh1 trrg tfrg 0.9v dd 0.1v dd symbol t rh1 t fh1 t rrg t frg xh1 rise time xh1 fall time rg rise time rg fall time 2 2 2 2 ns ns ns ns definition typ. unit (v dd = 5.0v, topr = 25 c, load capacity of xh1 = 10pf, load capacity of rg = 10pf) waveform characteristics of xh1 and rg
9 CXD2408AR vri hdo vdo vdo f h f h l: odd h: even tp1 tp2 tp3 tp4 tp5 odd even 259h 259h 2 1 1 2 symbol t p1 t p2 t p3 t p4 t p5 range of resetting to odd range of resetting to even range of resetting to odd prohibited area prohibited area 21.9 31.6 9.7 200 200 s s s ns ns definition specified value unit in the normal reset mode, the signal output is reset to odd or even field depending on the input timing of the vertical reset signal as shown in the figure below. field identification
10 CXD2408AR vri hdo vdo vdo f h f h l: odd h: even tp1 tp2 tp3 tp4 tp5 odd even 1 2 2 1 symbol t p1 t p2 t p3 ? t p4 t p5 range of resetting to odd range of resetting to even range of resetting to odd prohibited area prohibited area 21.9 31.6 200 200 s s s ns ns definition specified value unit in the direct reset mode, the signal output is reset to odd or even field depending on the input timing of the vertical reset signal as shown in the figure below. field identification ? in the direct reset mode, the cycle of hd can be arbitrary. therefore, t p3 is not specified.
11 CXD2408AR description of operation 1. mode control symbol rm rdm ps ext rend revh 42 41 3 36 37 38 1/30s non-interlaced normal operation parallel internal synchronization normal reset v reset 1/60s interlaced random trigger shutter serial external synchronization direct reset hv reset electronic shutter speed input method pin no. l h remarks 2. mode relationships rm l 1/30s non-interlaced l internal synchronization lh normal operation random trigger shutter normal operation h direct reset l normal reset external synchronization h h 1/60s interlaced l internal synchronization lh normal operation random trigger shutter normal operation l v reset h hv reset external synchronization h ext rdm rend revh : disabled direct reset l h v reset hv reset
12 CXD2408AR 3. electronic shutter smd1 smd2 l l flickerless: eliminates fluorescent frequency-induced flicker. l h high-speed shutter: shutter speed faster than 1/60 h l low-speed shutter: shutter speed slower than 1/60 h h no shutter operation ps = low : parallel input; set by ed0 to ed2, smd1, and smd2. ps = high : serial input; set by inputting ed0 (strobe), ed1 (clock), and ed2 (data) to each pin. 3-1. parallel input shutter speed compatibility chart mode off flickerless l l l l l l l l l l l l l l l l l l h l l l l l l l l l h h h h h h h h h l h h h h h h h h l l l l l l l l x x h l h l h l h l h l h l h l h l x x h h l l h h l l h h l l h h l l x x h h h h l l l l h h h h l l l l shutter off ? 1/100 (s) 1/60 (s) 1/125 (s) 1/250 (s) 1/500 (s) 1/1000 (s) 1/2000 (s) 1/4000 (s) 1/10000 (s) 2fld 4fld 6fld 8fld 10fld 12fld 14fld 16fld high-speed shutter low-speed shutter ps smd1 smd2 ed0 ed1 ed2 shutter speed ? shutter speed is 1/30s in 1/30s mode, and 1/60s in 1/60s mode.
13 CXD2408AR 3-2. serial input for serial input (ps = high), smd1 and smd2 bits within ed2 (data) take priority over smd1 (pin 7) and smd2 (pin 9) pins as smd1 and smd2 (shutter mode control). in this case, control by smd1 and smd2 pins is invalid. smd1 smd2 dummy d0 d1 d2 d3 d4 d5 d6 d7 d8 ed1 (clk) ed2 (data) ed0 (stb) ed2 data is latched to the register at the rise of ed1, and transferred to the within at the rise of ed0. ac characteristics ed2 ed1 ed0 ts2 th2 tw1 ts1 tw0 ts0 symbol definition t s2 t h2 t s1 t w0 t s0 t w1 ed2 set-up time, activated by the falling edge of ed1 ed2 hold time, activated by the rising edge of ed1 ed1 rising set-up time, activated by the rising edge of ed0 ed0 pulse width ed0 rising set-up time, activated by the rising edge of ed1 ed1 pulse width (serial input) 20ns 20ns 20ns 20ns 20ns 20ns 50s min. max.
14 CXD2408AR 3-3. shutter speed calculation formula high-speed shutter t = [262 10 (1ff 16 l 16 )] 63.56 + 34.78 (s) ( ? l 16 = load value) load value 0fa 16 0fc 16 100 16 108 16 118 16 137 16 176 16 196 16 1/10000 1/4000 1/2000 1/1000 1/500 1/250 1/125 1/100 1/10169 1/4435 1/2085 1/1012 1/499 1/252 1/125 1/100 shutter speed calculated value low-speed shutter n = 2 (1ff 16 l 16 ) fld however, the load value of ff 16 cannot be used . load value 1fe 16 1fd 16 : 101 16 100 16 2 4 : 508 510 shutter speed (fld) ? in case of starting with serial input setting (ps = h), be sure to transfer shutter speed data in the range of specification after power is turned on, and then use it..
15 CXD2408AR 4. random trigger shutter the random trigger shutter is different from the conventional electronic shutter in that the exposure beginning can be freely set. the exposure period (shutter speed) can be set as with the conventional electronic shutter. in this mode, xsub rises for each 1h, and the charge stored in the sensor is discharged. because the v clock (xv1 to xv3) is continuously operating, any unneeded charge in the vertical ccd is eliminated. xsg pulse is stopped until the external trigger is detected. the image cannot be monitored until the external trigger is detected and the signal is read out. when an external trigger is input in this state, hd is forcibly reset when the trigger falls, and xsub falls once to clear the charge and then halts. xv1 to xv3, xcpdm, xcpob, and pblk are reset with hd. from this point, exposure begins, and after the preset exposure period has passed, the xsg pulse falls, the charge is transferred from the sensor to the vertical ccd, and exposure ends. the xsg pulse falls with the time set as in conventional electronic shutters, regardless of vd. because hd is reset, the exposure period is accurate in 1h units. the wen pulse is generated synchronously with the xsg pulse. as the wen pulse specifies the signal start, it can be used as the sync signal for writing image data into the frame memory. in the random trigger shutter mode, v-direction functions of a sync signal generator are halted. as a result, sync signals vd and fld are also halted. hd reset xsub reset shutter speed trig hd xsub xv1 xv2 xv3 wen xsg
16 CXD2408AR 5. external synchronization - reset hd and vd are reset to synchronize with the external sync signal. resetting is done to synchronize a plural number of camera systems whose clock frequencies are the same. there are two reset inputs: hri and vri. when their falling edge is detected, resetting is carried out. the CXD2408AR has two reset modes: normal reset and direct reset. details of the reset modes are described in the following pages. in the 1/30s non-interlaced readout mode, the normal reset mode is not supported, and although the direct reset mode is supported, the field is not identified.
17 CXD2408AR 57.1 to 57.2s (701 to 702 bit) reset 6.3 to 6.37s hri hd out h reset hri hdo vri vdo hri hdo vri vdo 9h 259h 9h 259h field.o field.e field.o field.e 5-1. normal reset in the normal reset mode, the reset signal is input for resetting, and the sync signal is output continuously from that time. only the mode which resets both hd and vd (hv reset) is supported. when the h reset signal hri is continuously with an h cycle, resetting is triggered at the first falling edge, and after that point no resets are triggered at edges unless hd after resetting exceeds 2bits (163ns) on the internal clock. in other words, the hri input jitter is absorbed when it is up to 163 ns. the hri minimum reset pulse width is 0.3s. in the v direction, counting begins from vri fall, and v is reset to cause vdo to fall after 262.5 3.5 = 259h. the vri minimum reset pulse width is 2h. resetting is done for odd or even field, depending on the input timing of the v reset signal. the identification timing is shown in electrical characteristics (field identification).
18 CXD2408AR 5-2. direct reset in the direct reset mode, when the reset signal is input for resetting, a sync signal is output, but there is no continuous output. there are two direct reset modes: one to direct reset vd only (v reset), and one to reset both hd and vd (hv reset). (however, note that even for v reset, the hri signal is acceptable and the reset timing is the same as in normal reset mode.) in both modes, the vd reset timing is the same. when the external input v reset signal vri fall is detected, a judgment is made as to odd or even. if odd, v is reset to cause vdo to fall simultaneously with hd fall, and if even, v is reset to cause vdo to fall simultaneously in the middle of hd. vri requires a minimum pulse width of 2h. h direct reset detects the fall of h reset signal hri, and resets h so that hdo falls at the next cl falling edge. the minimum hri reset pulse width is 0.3s. resetting is done for odd or even field, depending on the input timing of the v reset signal. the identification timing is shown in electrical characteristics (field identification). 5-2-1. v reset hri hdo vri vdo hri hdo vri vdo 9h 9h field.o field.e field.o field.e
19 CXD2408AR 5-2-2. hv reset (1/60s interlaced readout mode) hdo hri vdo vri xsg id hdo hri vdo vri xsg id hdo field.o field.e cl hri 9h 9h field.e field.o
20 CXD2408AR 5-2-3. hv reset (1/30s non-interlaced readout mode) hdo hri vdo vri xsg id hdo hri vdo vri xsg id 9h hdo cl hri 9h
21 CXD2408AR timing chart (1) 1/60s interlaced readout (rm = high) 1 5 fld vdo xv1 xv2 xv3 out1 out2 xsg xvhold xvog xhhg1a xhhg1b xhhg2 pblk xcpob xcpdm id wen hdo blk 493 494 1 2 3 4 5 6 7 8 2 4 6 8 10 12 14 16 1 3 5 7 9 11 13 525 493 494 3 7 1 5 3 7 9 13 11 15 2 6 4 8 2 6 4 8 10 14 12 16 270 275 280 285 15 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 260 261 262 263 264 265
22 CXD2408AR timing chart (2) 1/30s non-interlaced readout (rm = low) 1 2 3 4 5 6 7 8 1 2 3 4 fld vdo blk hdo xv1 xv2 xv3 out1 xsg xvhold xvog xhhg1a xhhg1b xhhg2 pblk xcpob xcpdm id wen 493 1 2 3 4 5 6 7 8 1 2 3 494 493 494 525 525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
23 CXD2408AR timing chart (3) 1/60s interlaced readout (rm = high) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 blk/hd cl xhhg1a xv1 xv2 xv3 xvhold xvog xhhg1b xhhg2 xh1 xh2 rg xshp xshd xsub pblk xcpob xcpdm id wen opb (31 bits) 35 53 41 47 47 71 59 77 89 95 65 83 65 83 37 52 78 89 95 35 35 63 59 77 77 95 47 76 101 101 100 75 56 72 95 115 93 93 35 31 13 dummy (16 bits) opb (2 bits) 78 132 69 114 105 58
24 CXD2408AR timing chart (4) 1/30s non-interlaced readout (rm = low) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 blk/hd cl xhhg1a xv1 xv2 xv3 xvhold xvog xhhg1b xhhg2 xh1 xh2 rg xshp xshd xsub pblk xcpob xcpdm id wen opb (31 bits) 35 47 59 77 89 65 35 35 95 101 100 72 95 115 105 93 93 35 31 13 dummy (16 bits) opb (2 bits) 89 59 65 35 78 132 114
25 CXD2408AR timing chart (5) 1/60s interlaced (rm = high) hd xv1 xv2 xv3 xsg xv1 xv2 xv3 xsg odd field even field 42.4s (520 bits) 16.1s (198 bits) 2.53s (31 bits) 2.94s (36 bits) 2.53s (31 bits) timing chart (6) 1/30s non-interlaced (rm = low) hd xv1 xv2 xv3 xsg odd field 42.4s (520 bits) 16.1s (198 bits) 2.53s (31 bits) 2.94s (36 bits) 2.53s (31 bits)
26 CXD2408AR timing chart (7) hd cki cl xh1 xh2 rg xshp xshd xrs cld
27 CXD2408AR timing chart (8) hdo vdo sync blk fld field e field o o : odd e : even 9h 20h hdo vdo sync blk fld 9h 20h field e field o
28 CXD2408AR timing chart (9) hdo blk hsync eq vsync vdo fld 2fh fh odd even 6.36s (78 bits) 4.89s (60 bits) 2.45s (30 bits) 26.89s (330 bits) 4.89s (60 bits) 63.56s (780 bits) 1/2h 31.78s (390 bits) 9.86s (121 bits) 11.82s (145 bits) 10.14s (124 bits) 9.78s (120 bits) 22.00s (27 bits) 1.47s (18 bits) 10.76s (132 bits)
29 CXD2408AR CXD2408AR 12p 20p 1000p 0.01 10/10v 2.2k 47p 47p 2.2k 47p 2.2k 47p 2.2k 47p 2.2k 0.01 10/10v 47p 2.2k 47p 2.2k 47p 2.2k 74hc04 cxd1250m vsub adj. n.c. n.c. n.c. n.c. n.c. n.c. icx074ak/al cxa1690q cxa1690q cxd2311ar cxd2311ar n.c. n.c. 47p 2.2k 47p 2.2k n.c. n.c. to memory controller n.c. ccd out1 ccd out2 analog out1 analog out2 digital out1 (10bit) digital out2 (10bit) 13 14 15 21 22 24 22 22 13 14 15 21 24 22 +5v input only for random trigger shutter mode. cxd1268m 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 1 application circuit (1/60s interlaced, internal synchronization, normal continuous operation) application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
30 CXD2408AR package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin plating 42/copper alloy package structure 12.0 0.2 ? 10.0 0.1 (0.22) b 1 16 17 32 33 48 49 64 0.1 0.1 0.5 0.2 0 to 10 64pin lqfp (plastic) lqfp-64p-l01 lqfp064-p-1010 0.3g detail a 0.5 0.2 (11.0) a 1.5 0.1 + 0.2 0.1 solder/palladium note: dimension " ? " does not include mold protrusion. 0.13 m 0.5 b = 0.18 0.03 ( 0.18 ) (0.127) + 0.08 0.127 0.02 + 0.05 detail b : solder b = 0.18 0.03 0.125 0.04 detail b : palladium sony corporation

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